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device description the device, whose internal block diagram is shown in figure 1, is an integrated circuit realised in bcd technology. it is a controller for a synchronous-rectified buck converter operating in voltage mode, which provides all the features (a five bit digital to analog converter, an high performance error amplifier, a built-in programmable oscillator) needed to implement and properly control a vrm smps for advanced microprocessor supplies with a minimum components count. it is available in so20 package. the most significant features of the device are the following points: ttl-compatible 5 bit programmable output from: 1.3v to 2.05v with 0.05 binary steps; 2.1v to 3.5v with 0.1 binary steps; voltage mode pwm control; excellent output accuracy +/-1% over line, and temperature variations; digitally trimmed high precision internal reference; june 2000 ? AN1135 application note designing with l6911b, 5 bit step down controller the increase of computing capability and the consequential rising in complexity of modern microproc- essors have lead to the reduction of the supply voltages, the increase of the clock frequency and of the current required. the l6911b is a new pwm controller specifically designed to provide a high performance dc-dc conversion for advanced microprocessors. this paper deals on how to use this device in design ap- plications. pgnd phase gnd vfb lgate boot ugate vcc ocset vcc 12v vin 5v vo 1.8v to 3.5v pgood comp vsen ss ovp rt vd0 vd1 vd2 vd3 vd4 monitor and protection osc d/a e/a pwm + - - + d99in1043 figure 1. internal block diagram. 1/14
operating supply voltage from 5v or 12v; very fast load transient 0% to 100% duty cycle; power good output; overvoltage protection; overcurrent protection realised using the upper mosfet's rdson; operating frequency from 50khz to 1mhz; disable function. pins description n pin function 1 vsen connected to the output is able to detect overvoltage conditions and the pgood signal. this pins is not used for the feedback. 2 ocset a resistor connected from this pin and the upper mos drain sets the current limit protection. the internal 200 m a current generator sinks a current from the drain through the external resistor, generating a threshold that is compared with the mos drop. to reduce noise and avoid undesirable triggering a small ceramic capacitor has to be connected in parallel to the resistor. 3 ss the soft start time is set connecting an external capacitor between this pin and gnd. the internal current generator forces 10 m a through the capacitor. this pin can be used to disable the device forcing a voltage lower than 0.4v. 4-8 vid0-4 voltage identification pins. these open collector inputs (ttl compatible) are internally pulled up. they are used to program the output voltage as specified in the table of the datasheet. they set also the powergood and the overvoltage threshold. 9 comp this pin is connected to the error amplifier output to compensate the feedback loop. 10 fb this pin is connected to the error amplifier inverting input. the non inverting input of the error amplifier is connected to the dac output. 11 gnd all internal voltage references are referred to this pin. 12 pgood this pin is an open collector output and it is forced low if the output voltage is not within +/-10% of the programmed one. vsen ocset ss vid0 vid1 vid3 vid2 vid4 comp pgood phase ugate pgnd boot lgate vcc ovp rt 1 3 2 4 5 6 7 8 9 18 17 16 15 14 12 13 11 19 10 20 fb gnd d98in958 figure 2. pin out. AN1135 application note 2/14
n pin function 13 phase this pin is connected to the source of the upper mos and provides the return path for the high side driver. this pin monitors the drop across the upper mos for the current limitation. 14 ugate high side gate driver output. a resistor connected between this pin and the power mos gate can be used to reduce the peak current. 15 boot bootstrap capacitor pin. the bootstrap capacitor must be c onnected between this pin and phase; the boot diode must be connected between his pin and v cc 16 pgnd power ground pin. this pin has to be connected closely to the low side mos source in order to reduce the noise injection into the device. 17 lgate low side gate driver output. a resistor connected between this pin and the power mos gate can be used to reduce the peak current. 18 vcc connected this pin to the 12v or 5v bus it provides the device bias supply. a capacitor has to be connected between this pin and pgnd close to the device, to supply the impulsive current requirement of the lower driver. do not connect v in to 12v if v cc is 5v. 19 ovp over voltage protection. if the output voltage reaches the 15% above the programmed voltage, this pin is driven high and can be used to drive an external scr that shuts down the supply voltage. 20 rt oscillator switching frequency pin. connecting a resistor between this pin and gnd or v cc is possible to change the switching frequency. the voltage at this pin is fixed at 1.26v. forcing a 50 m a current at this pin the built in oscillator stops to switch. oscillator the switching frequency is internally fixed to 200khz. this value is suitable for a wide range of applications. however it can be varied using an external resistor (r t ) connected between r t pin and gnd or v cc . in particular connecting it to gnd the frequency is increased, in according to the following relationship (figure 3): f s = 200khz + 5 ? 10 6 r t [k w ] connecting r t to v cc = 12v or to v cc = 5v the frequency is reduced, in according to the follow- ing relationships (figure 3): f s = 200khz 4 ? 10 7 r t [k w ] if v cc = 12v, f s = 200khz 15 ? 10 6 r t [k w ] if v cc =5v the pwm ramp is generated charging and discharging an internal capacitor with a constant current. in practice the current delivered to the oscillator is varied from the standard value equal to 50 m a, allow- ing a switching frequency different from 200khz. thanks to the digital trimming of both the oscillator cur- rent and of the oscillator capacitor the maximum deviation of the switching frequency from the calculate value using the above equations is 15% for all the r t range (r t >6k w if connected to ground and r t > 200k w if connected to v cc = 12v). pins description (continued) 10 100 1000 frequency [khz] 10 100 1000 10000 resistance [kohm] rt to gnd rt to vcc=12v rt to vcc=5v figure 3. resistance vs. frequency AN1135 application note 3/14
digital to analog converter the built-in digital to analog converter allows the adjustment of the output voltage from 1.3v to 2.05v with 0.05v binary steps and from 2.1v to 3.5v with 0.1v binary steps. the internal reference is digitally trimmed, ensuring 1% precision (see the datasheet). the output voltage programming is reported in the datasheet. the voltage identification (vid) pin configuration also sets the power-good (pgood) and the over- volt- age protection (ovp) thresholds. the dac is realised by means of a series of resistors that provides a partition of the voltage reference. the vid code drives a multiplexer that selects a voltage on a precise point of the divider. the dac output is de- livered to an amplifier obtaining the vprog voltage reference (i.e. the set-point of the error amplifier). soft start at start-up a ramp is generated charging the external capacitor c ss by means of a 10 m a constant current, as shown in figure 4 (v in =v cc =5v,v out =3v, c ss = 100nf, without any load). when the voltage across the soft start capacitor v ss reaches 0.5v the lower power mos is turned on. as v ss reaches 1v (i.e. the oscillator tri angular wave in- ferior limit) also the uppermos begins to switch. the v ss growing voltage initially clamps the out- put of the error amplifier, and consequently v out linearly increases, as shown in figure 4. in this phase the system works in open loop. when v ss is equal to v comp the clamp on the output of the error amplifier is released. in any case another clamp on the input of the error amplifier remains active, allowing to v out to grow with a lower slope (i.e. the slope of the v ss voltage, see figure 4). in this second phase the system works in closed loop with a growing reference. as the out- put voltage reaches the desired value v prog also the clamp on the error amplifier input is removed, and the soft start finishes. the soft start pin is internally shorted to gnd until both v cc and ocset overcames the turn-on threshold. driver section figure 4. soft start, ch1 = v in ch2 = v ss ch3 = v comp ch4 = v out figure 5. ch1 = v lgate ch2 = i gate v cc =5v figure 6. ch1 = v lgate ch2 = i gate v cc =12v AN1135 application note 4/14
the high driver capability on the high and low side drivers allows to use different types of power mos (also multiple mos to reduce the r dson ), maintaining fast switching transition. in the pcb it is possible to mount up to three so8 power mos for both the low and the high side. the peak current is shown for both the lower (figures 5 and 6) and the upper (figure 7 and 8) driver at 5v and 12v. a 10nf capacitive load has been used in these measurements. for the lower driver the source peak current is 600ma@v cc = 5v and 2.3a@v cc = 12v, and the sink peak current is 1.2a@v cc = 5v and 3a@v cc = 12v. similarly or the upper driver the source peak current is 350ma@v cc = 5v and 1.6a@v cc = 12v, and the sink peak current is 650ma@v cc = 5v and 2.4a@v cc = 12v. monitor and protection the output voltage is monitored by means of pin 1 (v sen ). if it is not within 10% of the programmed value, the powergood output is forced low. the device provides overvoltage protection, when the output voltage reaches a value 15% grater than the nominal one. if the output voltage exceed this threshold, the ovp pin is forced high, triggering an ex- ternal scr to shuts the supply (v cc ) down, and the lower driver is turned on. to perform the overcurrent protection it compares the drop across the high side mos, due to the r dson , with the voltage across the external resistor (r ocs ) connected between the ocset pin and drain of the upper mos. thus the overcurrent threshold (i p ) can be calculated with the following relationship: i p = i ocs ? r ocs r dson where the typical value of i ocs is 200 m a (see the datasheet). to calculate the r ocs value it must be considered the maximum r dson (also the variation with temperature) and the minimum value of i ocs . substituting the parameters of the demo board (i ocsmin = 170 m a, r ocs =1k w ,r dsonmax =9m w ) in the equation above, i p results equal to 19a. to avoid undesirable trigger of overcurrent protection this rela- tionship must be satisfied: i p i outmax + d i 2 = i peak where d i is the inductance ripple current and i outmax is the maximum output current. in case of output short circuit the soft start capacitor is discharged and the system works in hiccup mode, as shown in figure 9 and 10 (ch1 = v ss and ch2 = inductor current). figure 7. ch1 = v ugate ch4 = i gate v cc = 5v figure 8. ch1 = v ugate ch4 = i gate v cc =12v AN1135 application note 5/14
application circuit figure 11 shows the schematic circuit of the evaluation board. the design has been developed for an output current up to 14a, as requested by new microprocessors. the device is supplied by the 12v input rail, and it is also able to operate with a 5v supply voltage; in this case 12v input can be directly connected to the 5v power source. also the main power source can be either +5v or +12v, changing the position of the fuse (see figure 11 and the pcb layout). figure 9. hiccup mode v cc =v in =5v figure 10. hiccup mode v cc =v in = 12v d99in1044 l2 l1 r6 r7 r8 r9 r1 r3 r4 r5 r2 c1-5 c21-22 c23 c24 c6-15 c25 c16 c18 c20 c19 q4-5 q1-2 d2 q8 d1 c17 f1 16 17 13 14 15 12 2 4 5 6 7 8 9 10 320111 18 19 +5 v in +12v in vid0 vid1 vid2 vid3 vid4 v out pwrgd figure 11. schematic circuit AN1135 application note 6/14
inductor the inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to sustain the output and the input voltage vari- ation to maintain the ripple current d i l between 20% and 30% of the maximum output current. in order to optimise the load transient response time, the current ripple is fixed to 30%. the inductance value can be calculated with this relationship: l = v in - v out f s ? d i l ? v out v in where f sw is fixed at 200khz to improve the efficiency, v in is the input voltage and v out is the output voltage. figure 12 shows the ripple current vs the output voltage for different values of the inductor value, with v in = 5v and v in = 12v. since the maximum output current is equal to 14a, to have a 30% ripple (4a) in worst case we have chosen a inductance equal to 3 m h. so the ripple is 4.1a@3.5v with v in = 12v and 1.7a@3.5v with v in = 5v. in worst case the peak current is 18.1a. output capacitor since the microprocessors require a current vari- ation beyond of 10a during load transients, with a slope in the range of tenth a/ m s, the output ca- pacitor is a basic component for the fast re- sponse of the power supply. in fact for first few microseconds the current to the load is supplied by them. the controller recognises immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the in- ductor value. the output voltage has a first drop due to the cur- rent variation inside the capacitor (neglecting the effect of the esl): d v out = d i out ? esr in the demo ten sanyo capacitors, model 6mv1000gx are used, with a maximum esr equal to 69m w . therefore the resultant esr is 69m w /10 = 6.9m w . for a load transient of 14a in worst case the drop re- sults: d v out = 14 ? 0.00069 = 96.6mv a minimum capacitor value is required to sustain the current during the load transient without discharge it. the voltage drop due to the output capacitor discharge is given by the following equation: d v out = d i out 2 ? l 2 ? c out ? ( v inmin ? d max - v out ) substituting the parameters and considering that d max is equal to 100%, for a load transient of 14a and v out equal to 2.5v, the drop results equal to 13mv. input capacitor the input capacitor has to sustain the ripple current produced during the on time of the upper mos, so it must have a low esr to minimise the losses. the rms value of this ripple is: 1.5 2.5 3.5 2.0 3.0 output voltage [v] 2 4 6 current ripple [a] vin =5v vin=12v l=4 m h l=3 m h l= 2 m h l= 4 m h l= 3 m h l=2 m h figure 12. inductor ripple current vs v out AN1135 application note 7/14
i rms = i out ? ````````` ` d - 2 ? h ? d 2 h + ? ? ? d h ? ? ? 2 where h is the expected efficiency and d is the duty cycle. for i out = 14a and with d = 0.5, in which the equation reaches his maximum value, i rms is equal to 7a. five sanyo electrolytic capacitors 25mv330gx, with a maximum esr equal to 69m w , are chosen to sustain this ripple. therefore the re- sultant esr is 69m w /5 = 13.8m w . so the losses in worst case are: p = esr ? i rms 2 = 670mw transient response the control loop is a voltage mode (figure 11 and figure 16) that uses a droop function to satisfy the re- quirements for a vrm module, reducing the size and the cost of the output capacitor. this method orecoverso part of the drop due to the output capacitor esr in the load transient, introduc- ing a dependence of the output voltage on the load current (figure 13 and 15): at light load the output voltage will be higher the nominal level, while at high load the output voltage will be lower the nominal value. as shown in figure 13, the esr drop is present in any case, but using the droop function the total devia- tion of the output voltage is minimised. in practice the droop function introduces a static error (vdroop in figure 13) proportional to the output current (see also figure 15). since a sense resistor is not present, the output dc current is measured by using the intrinsic resistance of the inductance (a few mw). so the low-pass filtered inductor voltage (that is the inductor current) is added to the feedback signal, imple- menting the droop function in a simple way. the static characteristic of the closed loop system is: v out = v prog + v prog ? ? ? ? r 3 + r 8 / /r 9 r 2 ? ? ? r l ? r 8 //r 9 r 8 ? i out where v prog is the output voltage of the digital to analog converter (i.e. the set point) and rl is the in- ductance resistance. the second term of the equation allows a positive offset at zero load; the third term introduces the droop effect. note that the droop effect is equal the esr drop if: r l ? r 8 //r 9 r 8 = esr in figure 15 this linear characteristics is compared with the measured behavior for an output current from 1a to 14a. a r l equal to 10m w has been substituted in the relationship above, considering the tempera- v max v min v nom (a) (b) d99in1045 esr drop esr drop v droop figure 13. output transient response without (a) and with (b) the droop function AN1135 application note 8/14
ture effect and the soldering of the choke (i.e. the increase of the inductance resistance). figure 14 shows the acquired waveforms of the output voltage for a 0-14a load transient. ch1 is the out- put voltage (with a 2v offset set on the scope) and the ch2 is the output current. compensation network figure 14. output transient response 2 4 6 8 10 12 14 16 output current [a] 1.95 2.00 2.05 2.10 output voltage [v] figure 15. static regulation c18 c20 c19 r5 r4 r3 r9 l2 esr c6-15 d99in1046 r8 r2 pwm c25 v in v prog r l z f z i z d v out v phase v comp figure 16. compensation network AN1135 application note 9/14
the compensation network is shown in figure 16. since the voltages v phase and v out are both taken in low impedance nodes, it is possible to calculate the transfer functions between v phase and v comp , and between v out and v comp by using superposition. neglecting the effect of r2 (i.e. the input of the error amplifier is a virtual ground) the following relationships can be written: v comp ( s ) v phase ( s ) = - 1 r 8 + z d ( s ) / / z i ( s ) ? z d ( s ) z d ( s )+ z i ( s ) ? z f ( s )= f ( s ) ? z d ( s ) v comp ( s ) v out ( s ) = - 1 z d ( s )+ r 8 / / z i ( s ) ? r 8 r 8 //z i ( s ) ? z f ( s )= f ( s ) ? r 8 where: f ( s )= z f ( s ) r 8 ? z d ( s )+ r 8 ? z i ( s ) + z i ( s ) ? z d ( s ) z f ( s )= 1 sc 18 // ? ? ? r 5 + 1 sc 19 ? ? ? ;z i ( s )= r 3 / / ? ? ? r 4 + 1 sc 20 ? ? ? ;z d ( s )= r 9 / / 1 sc 25 to continue the analysis we can use the system in figure 17, in which the pwm modulator gain m has been introduced: m = v in d v osc where d v osc is the ramp amplitude of the oscillator (typ. 1.9v). g(s) is the output lc filter block (i.e. l 2 and c tot =c 6 //c 7 //...c 15 ). f(s) z d (s) d99in1047 m g(s) f(s) mr8 h(s) figure 17. two loops control system AN1135 application note 10/14
referring to figure 17 the transfer function h(s) of the inner loop results: h ( s )= 1 1 - m ? f ( s ) ? z d ( s ) @ 1 m ? f ( s ) ? z d ( s ) the above approximation is possible if the inner loop gain is quite high (>>1). this condition is usually satisfied; in fact it is indispensable to have a good regulation and low audio susceptibility. h(s) gain crosses the 0 db axis at w h with a - 20db/dec slope, ensuring the loop stability. look- ing at the h(s) bode plot, it results equal to 0db beyond w h . a simple way to consider this behav- ior is adding a pole at w h : h ( s )= 1 m ? f ( s ) ? z d ( s ) ? ? ? ? 1 + s w h ? ? ? the calculation of the outer loop will be simplified: m and f(s) cancel, obtaining this expression: g loop ( s )= r 8 z d ( s ) ? g ( s ) ? 1 1 + s w h substituting all the terms: g loop ( s )= r8 ? 1 + sc25 ? r9 r9 ? 1 + sc tot ? esr s 2 l 2 c tot + sc tot ? ( esr + r l )+ 1 ? 1 1 + s w h the z d (s) pole becomes a zero, while the lc(s) singularities remain unaltered. a suitable choice for lo- cating the poles and the zeros of g loop (s) is: place the pole at w h for compensating the esr zero, and place the z d (s) pole for the desired transient response. in fact closing the loop the time constant r 9 c 25 becomes a pole of the entire system, and it fixes the time response. 10 1 10 2 10 3 10 4 10 5 10 6 10 7 -80 -60 -40 -20 0 20 40 60 80 [rad/s] module [db] figure 18. inner loop bode plot 10 1 10 2 10 3 10 4 10 5 10 6 10 7 -60 -40 -20 0 [rad/s] module [db] figure 19. h(s) bode plot 10 1 10 2 10 3 10 4 10 5 10 6 10 7 -40 -20 0 20 [rad/s] module [db] figure 20. system loop gain g loop (s) bode plot AN1135 application note 11/14
efficiency the measured efficiency versus load current for different values of output voltage is shown in fig- ure 16. the measures was done at v in = 5v for different values of the output voltage (2v and 2.8v). the supply voltage of the device v cc has always been connected directly to the power source v in (i.e. v cc =v in ). in the application two mosfets sts12nf30l (30v, 10m w typ. with v gs = 4.5v) connected in parallel are used for both the low and the high side. 2 4 6 8 10 12 14 16 output current [a] 70 75 80 85 90 95 efficiency [%] vin= vcc = 5v, vout =2.8v vin= vcc = 5v, vout =2v figure 21. efficiency vs. load figure 22. pcb and components layouts. AN1135 application note 12/14
1a 2a 3a 4a 5a 6a 7a 8a 9a 10a 11a 12a 13a 14a 15a 16a 17a 18a 19a 20a 1b 2b 3b 4b 5b 6b 7b 8b 9b 10b 11b 12b 13b 14b 15b 16b 17b 18b 19b 20b 5v in 5v in 5v in 12v in sense outen vid1 vid3 pwrgd v ss v cc core 5v in 12v in 12v in i share vid0 vid2 vid4 v ss v cc core v ss v cc core v ss v cc core v ss v cc core v ss v cc core v ss v ss v cc core v ss v cc core v ss v cc core v ss v cc core v cc core 5v in 5v in figure 23. connector pin orientation part list r2 r3, r7 r4 r5, r8 r6 r9 499k 1k 20 20k 10k 15k 1% 1% smd 0805 smd 0805 smd 0805 smd 0805 smd 0805 smd 0805 c1,c2,..c5 c6,c2,..c15 c16,c24,c25 c17 c18 c19 c20 c23 c21, c22 330 m 1000 m 100n 4.7 m 2.2n 8.2n 82n 1n 1 m sanyo - 25mv330gx sanyo - 6mv1000gx ceramic ceramic ceramic ceramic ceramic ceramic ceramic radial 8x20mm radial 8x20mm smd 0805 smd 1206 smd 0805 smd 0805 smd 0805 smd 0805 smd 1206 l1 l2 1.5 m 3 m t44-52 core, 7t-18awg t5052b core, 10t-16awg u1 l6911b stmicreolectronics so20 q1,q2,..q4 q8 sts12nf30l n.c. stmicroelectronics so8 to220 d1 d2 1n4148 stps3l25u stmicroelectronics stmicroelectronics dl-35 smb f1 251015a-15a littlefuse axial 532956-7 amp connector AN1135 application note 13/14
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com AN1135 application note 14/14

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